Bandgap reference (BGR) circuits are utilized in host integrated circuits (ICs) to generate temperature-stabilized (temperature independent) reference voltages that are used by other circuitry of the host ICs. Conventional BGR circuits are generally classified as current-mode BGR circuits and voltage-mode BGR circuits. Both types of conventional BGR circuits generate a temperature-stabilized reference voltage/current by way of combining two voltages/currents having two opposite temperature coefficients, where the two voltages/currents include a positive temperature dependent voltage/current that rises in proportion to increases in absolute temperature (sometimes referred to as Proportionate to Absolute Temperature (PTAT) voltages), and a negative temperature dependent voltage/current that decreases as the temperature rises (sometimes referred to as Complementary to Absolute Temperature (CTAT) voltage/current). The PTAT and CTAT partial voltage/currents are then combined such that the opposite (positive/increasing and negative/decreasing) temperature coefficients of the PTAT and CTAT voltage/currents function to cancel each other, whereby variations of the temperature-stabilized reference voltage are significantly reduced. The two types of conventional BGR circuits differ in that, in current-mode BGR circuits, the reference voltage is derived from the sum of PTAT and CTAT currents, and in voltage-mode BGR circuits, the reference voltage is derived from the sum of PTAT and CTAT voltages.
FIG. 14 depicts a conventional current-mode bandgap reference (BGR) circuit 50 that is described by Banba et al. in “A CMOS bandgap reference circuit with sub-1-V operation” (IEEE J. of Solid-State Circuits, vol. 34 pp. 670-674, May 1999). Current-mode BGR circuit 50 includes an operational amplifier (op-amp) 51, a current mirror circuit 52 including three matched current source devices P1, P2 and P3, a negative temperature coefficient (CTAT) stage 53, a positive temperature coefficient (PTAT) stage 54, and an output stage 55. Op-amp 51 is of a type exhibiting an infinite DC gain and zero offset voltage for the applicable operating conditions. Current source devices (e.g., matched PMOS transistors) P1, P2 and P3 have gate terminals connect to an output terminal of op-amp 51 such that devices P1, P2 and P3 are controlled by op-amp output signal OA-OUT to respectively pass currents I1, I2 and I3 to stages 53, 54 and 55. CTAT stage 53 includes a single diode D1 and a resistor R1 that are connected in parallel between device P1 and ground such that portions Ia1 and Ia2 of current I1 respectively pass through diode D1 and resistor R1. Partial current I1a is a CTAT current controlled by voltage Vf1 across diode d1. With this arrangement, diode D1 and resistor R1 are configured to generate a negative temperature dependent voltage Va (sometimes referred to as a complementary-to-absolute-temperature, or CTAT, voltage) that is proportional to voltage Vf1, and therefore decreases as the operating temperature of the host IC increases. PTAT stage 54 includes multiple parallel-connected diodes D2 (each diode matching diode D1), a resistor R2, and a resistor R3 that are connected between device P2 and ground such that a first portion 2a1 of current I2 passes through resistor R3 and diode D1, and a second portion 2a2 of current I2 passes through resistor R2. Partial current I2b is a PTAT current controlled by voltage Vf2 across diodes D2 and dVf across resistor R3. Resistors R1 and R2 are formed with matching resistance values. PTAT stage 54 generates a positive temperature dependent (aka, PTAT) voltage Vb that is made proportional to the thermal voltage VT (i.e., a positive temperature coefficient of 0.086 mV/° C.) by way of generating a voltage Vf2 across multiple (N) parallel-connected diodes D2. Negative temperature dependent voltage Va is passed to the non-inverting (+) input terminal of op-amp 51, and positive temperature dependent voltage Vb is passed to the inverting (−) input terminal of op-amp 51. With this arrangement, and by forming resistor R3 with an appropriate R1/R3 ratio and by forming diodes D2 with an appropriate number N of diodes, a linear compensation of the temperature dependence of currents I1 and I2 is achieved, and bandgap reference voltage Vref is therefore generated by passing current I3 through resistor R4, where the magnitude of voltage Vref is adjustable for different applications by way of changing the size of resistor R4 (i.e., Vref=R4 (Vf1/R2+dVf/R3). An advantage of this scheme is that current-mode BGR circuit 50 generates partial currents I1 and I2 using a balanced circuit and only one control loop implemented by a CMOS operational amplifier 51.
In practical applications, a problem associated with conventional current-mode BGR circuit 50 is that the output current I3 is inherently mismatched with currents I1 and I2 due to differences in VDS of the current source devices P1, P2 and P3. Further, conventional current-mode BGR circuit 50 is subject to the low frequency (1/f) noise and to random threshold voltage variations between current source devices P1, P2 and P3, and also at the inputs of op-amp 52. One possible approach for removing the mismatch between output current I3 and currents I1 and I2 is to configure PTAT stage 54 and output stage 55 such that positive temperature dependent voltage Vb is equal to reference voltage Vref. While this solution approach may be theoretically possible, it is impractical because it would significantly increase the size (silicon area) occupied by the BGR circuit by way of requiring an extra op-amp circuit, and precludes the option of selectively setting the desired value of Vref (i.e., by way of implementing resistor R4 with different voltages) without sacrificing accuracy. Another approach may be to utilize the cascoding technique to increase the output impedance, but this solution is very limited in low power supply (sub-1V) voltage applications (e.g., 1V or less). The 1/f (aka “flicker”) noise problems caused by random noise variations and random threshold voltage variations in the current mirror, traditionally, are addressed by enlarging the sizes of the current source devices P1, P2, P3 devices (i.e., because the Vth mismatch is inversely proportional to square root of gate area and flicker noise power is inversely proportional to gate area). However, this solution is costly both in terms of silicon area (i.e., the size of the BGR circuit is greatly increased) and extra parasitic capacitance. Another possible approach is to increase the gate-source voltage of the PMOS current source devices with the purpose of increasing the overdrive voltage, making Vth a smaller fraction of the total Vgs (see M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching properties of MOS transistors”, IEEE Journal of Solid-state Circuits, vol. SC-24, pp. 1433-1440, 1989). However, as mentioned above, this solution “eats” into the headroom of the current source devices that defeats the purpose of having low voltage supply-based BGR.
What is needed is a BGR circuit that overcomes the above-mentioned deficiencies of conventional BGR circuits. In particular, what is needed is a BGR circuit that facilitates the use of low (e.g., sub-1V) supply voltages without requiring a significant increase in the chip area occupied by the BGR circuit, and also facilitates choosing a desired voltage reference level without sacrificing accuracy.